Staff Engineer, ASIC IP STA

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration. 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 + successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment .