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Silicon Roles

Synthesis & STA Engineer – High-Speed SerDes

Astera LabsSan Jose, California, United States$160,000–$200,000Physical DesignAnalog & Mixed-Signal
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The published floor of $160,000 is 10% below the Physical Design median of $177,500. First seen on this site 2026-10-28, open 13 days.
Posted 2026-11-01 · read from greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About Astera Labs Astera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. Our semiconductor-based platforms help solve signal, data, and memory connectivity bottlenecks in the world’s most demanding computing systems. Overview As an Astera Labs Synthesis & STA Engineer – High-Speed SerDes you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of high-speed analog/mixed-signal SerDes and connectivity ASICs used in the world's leading cloud service providers, server, and network OEMs.