SOC DFT Intern - Spring 2027

Job Title: DFT Intern Location: Austin, TX (On-site/Hybrid) Department: Digital Design – DFT Reports To: DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design for Test (DFT) Intern to join our Digital Design team. As a DFT Intern, you will work closely with experienced engineers to support the development and implementation of DFT methodologies for cutting-edge SoC designs. This internship offers hands-on experience in scan insertion, ATPG, MBIST, and other test-related flows in a real-world semiconductor environment. Key Responsibilities: Assist in the implementation of DFT techniques such as scan insertion, boundary scan, and memory BIST. Support ATPG pattern generation and validation using industry-standard tools. Help with test coverage analysis and debug of test patterns. Collaborate with RTL designers and verification teams to ensure testability requirements are met. Contribute to automation of DFT flows using scripting languages (e.g., Python, Perl, TCL). Document DFT methodologies, test plans, and results. Qualifications: Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Strong understanding of digital logic design and VLSI fundamentals. Familiarity with Verilog/VHDL and scripting languages (Python, Perl, or TCL). Exposure to DFT concepts such as scan chains, ATPG, and BIST is a plus. Experience with EDA tools from Synopsys, Cadence, or Mentor Graphics is desirable. Excellent problem-solving skills and attention to detail.